Static random access memory (SRAM) is an essential component in computer processor based systems. SRAM chips typically include millions of individual storage cells which each store a single digital bit value. Prior art SRAM cells have typically been single-ported, meaning that the cell may be read from and written to via a single write path. Recently, however, multi-port SRAM cells have become common in applications that require multiple data transfers into and out of memory during a single machine cycle, and in applications where the data to be stored comes from several different sources. Typical applications for multi-port SRAM arrays include high-speed general purpose registers used in a central processing unit (CPU), and high-speed cache memories used in instruction and data memory management. Multi-port SRAMs have n data input/output (I/O) ports and allow n separate data transfers during a single read or write cycle.
SRAMs are generally implemented as an array of individual storage cells. In the most basic SRAM array, the number of rows matches the number of addressable words in the memory and the number of columns matches the number of bits in each word. In this configuration, a wordline mapped to a given address activates a pair of pass gates of each storage cell in the addressed row to couple the respective storage cell to a different respective bitline. For read operations, a wordline for a given word is activated, and the stored data bit from each storage cell is coupled via the cell's enabled pass gates onto the storage cell's respective bitlines. In write operations, data is coupled onto the each of the respective bitlines and the wordline corresponding to the addressed word is activated to enable the cell's pass gates to couple the data present on the bitlines into each of the respective storage cell in the addressed row. In this addressing scheme, each bitline is coupled to every cell in a given column. In large SRAM arrays, this configuration results in very long bitlines, and therefore longer storage cell access time. Accordingly, modem SRAM arrays use column interleaving in order to provide a more square array configuration, and therefore minimize the bitline length and storage cell access time.
Column interleaving is also employed to reduce bit error rates by distributing each bit of a given word across different areas of the array. Generally speaking, storage cells within the same area of an SRAM chip are each susceptible to common corruption events. Storage cell corruption often occurs, for example, as a result of an electrostatic discharge (ESD) event or by bombardment of an alpha-particle. These events affect a much larger area of the chip than is occupied by a single storage cell. Accordingly, by interleaving memory bits across different portions of the memory chip, the probability that a number of adjacent bits in the same word experience corruption from the same event is reduced. Thus, if a corruption event occurs, generally only a single or a small few bits in any given word become corrupted. The column interleaving technique allows standard error correction techniques, such as parity checking and error correction code (ECC), to be used to recover each corrupted byte or word when a corruption event occurs because only a single or few bits are likely to become corrupted at any given time.
SRAMs are word-addressable, meaning that all storage cells that store a bit in a common word are accessed simultaneously. In a multiple write port SRAM array, bits in any given word may be accessed via different write ports of each storage cell. Each write port of each storage cell is activated by an independent wordline signal. Accordingly, because a single wordline signal activates the write ports of as many SRAM cells as there are bits in the word, if any bit is read from a different port than any of the other bits in the word (e.g., when different bits in a given word are to be written to from different sources or during different clock cycles and hence via different write ports), the write ports of some cells may be activated even though no data is actually being written to that cell via that port. This is referred to in the art as a "dummy read". Dummy reads, due to the additional charge placed on the storage node of the storage cell as a result of pre-charging the bitlines, often results in unintended flipping of the value stored by storage cells performing a dummy read. Accordingly, for stability reasons, multi-port SRAMs are generally implemented using differential circuit techniques, which require two bitlines and two access transistors to write a storage cell rather than one bitline and one access transistor for single-ended storage cells.
In the prior art SRAM cells, each additional write port requires an additional differential pair of bitlines and another set of associated bitline selection circuitry. The penalty for adding additional write ports to a storage cell in an SRAM is thus a large increase in the size of the SRAM circuitry.
A need exists for a multiple write port single-ended SRAM cell that minimizes the number of bitlines, selection circuitry, and storage cell components required in implementing the SRAM.